View 74LVQ273TTR_5340307.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/13 july 2004 high speed: f max = 150 mhz (typ.) at v cc = 3.3 v compatible with ttl outputs low power dissipation: i cc = 4 a (max.) at t a =25c low noise: v olp = 0.4v (typ.) at v cc = 3.3v 75 ? transmission line driving capability symmetrical output impedance: |i oh | = i ol = 12ma (min) at v cc = 3.0 v pci bus levels guaranteed at 24 ma balanced propagation delays: t plh ? t phl operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) pin and function compatible with 74 series 273 improved latch-up immunity description the 74lvq273 is a low voltage cmos octal d-type flip flop with clear fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and low noise 3.3v applications. information signals applied to d inputs are transferred to the q outputs on the positive going edge of the clock pulse. when the clear input is held low, the q outputs are held low independently of the other inputs. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvq273 octal d-type flip flop with clear figure 1: pin connection and iec logic symbols table 1: order codes package t & r sop 74lvq273mtr tssop 74LVQ273TTR tssop sop rev. 5
74lvq273 2/13 figure 2: input and output equivalent circuit table 2: pin description table 3: truth table x : don?t care figure 3: logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1clear asynchronous master reset (active low) 2, 5, 6, 9, 12, 15, 16,19 q0 to q7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 d0 to d7 data inputs 11 clock clock input (low-to-high edge triggered) 10 gnd ground (0v) 20 v cc positive supply voltage inputs output function clear dclockq l x x l clear hl l hh h hx q n no change
74lvq273 3/13 table 4: absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied table 5: recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2v table 6: dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 75 ? symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 400 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 3.0v (note 2) 0 to 10 ns/v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 3.0 to 3.6 2.0 2.0 2.0 v v il low level input voltage 0.8 0.8 0.8 v v oh high level output voltage 3.0 i o =-50 a 2.9 2.99 2.9 2.9 v i o =-12 ma 2.58 2.48 2.48 i o =-24 ma 2.2 2.2 v ol low level output voltage 3.0 i o =50 a 0.002 0.1 0.1 0.1 v i o =12 ma 0 0.36 0.44 0.44 i o =24 ma 0.55 0.55 i i input leakage current 3.6 v i = v cc or gnd 0.1 1 1 a i cc quiescent supply current 3.6 v i = v cc or gnd 44040 a i old dynamic output current (note 1, 2) 3.6 v old = 0.8 v max 36 36 ma i ohd v ohd = 2 v min -25 -25 ma
74lvq273 4/13 table 7: dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. table 8: ac electrical characteristics (c l = 50 pf, r l = 500 ? , input t r = t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh = |t plhm - t plhn |, t oshl = |t phlm - t phln |) 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l = 50 pf 0.4 0.8 v v olv -0.8 -0.5 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v v ild dynamic low voltage input (note 1, 3) 3.3 0.8 v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time ck to q 2.7 7.3 12.0 14.0 16.0 ns 3.3 (*) 6.0 9.0 10.5 12.0 t phl propagation delay time clr to q 2.7 9.8 15.5 18.0 21.0 ns 3.3 (*) 8.6 12.5 14.5 16.5 t w clear pulse width 2.7 5.0 2.5 5.0 5.0 ns 3.3 (*) 4.0 2.2 4.0 4.0 t w clock pulse width 2.7 5.0 2.0 5.0 5.0 ns 3.3 (*) 4.0 1.6 4.0 4.0 t s setup time d to ck, high or low 2.7 4.0 -0.4 4.0 5.0 ns 3.3 (*) 3.0 -0.3 3.0 4.0 t h hold time d to ck, high or low 2.7 3.0 0.4 3.0 3.5 ns 3.3 (*) 2.0 0.3 2.0 2.5 t rem recovery time clear to clock 2.7 4.0 -0.1 4.0 4.5 ns 3.3 (*) 3.0 0.0 3.0 3.5 f max maximum clock frequency 2.7 60 150 50 50 mhz 3.3 (*) 90 190 70 70 t oslh t oshl output to output skew time (note1, 2) 2.7 0.5 1.0 1.0 1.0 ns 3.3 (*) 0.5 1.0 1.0 1.0
74lvq273 5/13 table 9: capacitive characteristics 1) c pd is defined as the value of the ic?s internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8 (per flip flop) figure 4: test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 500 ? or equivalent r t = z out of pulse generator (typically 50 ? ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 3.3 5 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 30 pf
74lvq273 6/13 figure 5: waveform - propagation delays, setup and hold times clock pulse width (f=1mhz; 50% duty cycle) figure 6: waveform - propagation delays (f=1mhz; 50% duty cycle)
74lvq273 7/13 figure 7: waveform - recovery time, clear pulse width (f=1mhz; 50% duty cycle)
74lvq273 8/13 dim. mm. inch min. typ max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k0 8 0 8 ddd 0.100 0.004 so-20 mechanical data 0016022d
74lvq273 9/13 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0? 8?0? 8? l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
74lvq273 10/13 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 10.8 11 0.425 0.433 bo 13.2 13.4 0.520 0.528 ko 3.1 3.3 0.122 0.130 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel so-20 mechanical data
74lvq273 11/13 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.8 7 0.268 0.276 bo 6.9 7.1 0.272 0.280 ko 1.7 1.9 0.067 0.075 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop20 mechanical data
74lvq273 12/13 table 10: revision history date revision description of changes 29-jul-2004 5 ordering codes revision - pag. 1.
74lvq273 13/13 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of 74LVQ273TTR

	To Download 74LVQ273TTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .